19 May

Design Eng - Greater Noida - Stmicroelectronics

Position
Design Eng
Company
Stmicroelectronics
Location
Greater Noida UP
Opening
19 May, 2017 10 days ago

Stmicroelectronics as the company that open the jobs vacancy, have some qualification and spesification especially for the Design Eng jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Stmicroelectronics company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.

The ASIC Physical Implementation Design position is located at the STMicroelectronics site in Noida (India).
In this position, the ASIC Physical Implementation Designer covers all the steps from Netlist to Tape Out for complex digital ICs designed using leading edge technologies (28nm, 16nm, 7nm).
He/she has to manage the following tasks that are part of the ASIC implementation flow:
Pad Ring Definition / Pin assignment
Floorplanning and Block Placement
Power Routing
Cell Placement
Clock Tree Synthesis
Routing global, detailed, post route optimization, custom route
Full chip assembly and integration
Full Custom Layout as necessary
Layout Extraction, Back Annotation and Delay Calculation
Layout Verification (DRC/LVS/DFM), EM checking, Power Analysis
Timing Closure at subchip and full-chip level ECO timing loops ECO power loop
Functional ECO (full mask set and metal mask only)
Chip Finishing (FEOL tiles / BEOL tile / Embedded metrology)

Education Level Required: Graduated, Years of Work Experience: 2 to 5+
Good English. Experience in contacting/supporting external customers is appreciated.
Verilog/VHDL basic language knowledge is requested.

The knowledge on CAD tools for ASIC layout design, verification, floorplanning and timing analysis from vendors such as Synopsys, Cadence, Mentor Graphics are an asset for this position:
Cadence Innovus
Synopsys ICC2
Mentor Calibre
Synopsys Design Compiler
Synopsys PrimeTime
Synopsys Formality
Cadence Tempus

In addition, basic knowledge on DFT tools as following ones is appreciated:
Synopsys Test Compiler, Synopsys DFT Compiler, Synopsys Tetramax

It is recommended a good knowledge of linux operating system, cshell and tcl language

Profile

Education Level Required - M.Sc(Electronics), Years of Work Experience - 2 to 5,.

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