Physical Design Methodology Expert - Bangalore - Infneon Technologies India
Infneon Technologies India as the company that open the jobs vacancy, have some qualification and spesification especially for the Physical Design Methodology Expert jobs vacancy. To find out more information and about qualification and spesification details, walkin interview schedule, the address of the company, the company contact info (email/phone number) of Infneon Technologies India company, please start to apply for the job vacancy with fill the jobs application with click the 'Apply This Job' button below.
In your new role you will:
- Working with the team of SOC design methodology, flow and implementation engineers.
- Work on Synthesis, Floorplan, Powerplan, Place & Route, Clock Tree Synthesis, DFY/DFM and timing closure for complex designs.
- Development of technology files for place and route tool.
- Work closely with Timing methodology/signoff team and design teams to improve the flow which helps faster timing closure.
- Responsible for debugging current tool and flow issues working closely with EDA vendors and drive them for new features.
- Adapting Infineon flow and tools for faster and reliable tape out of complex designs. Work as integral part of the team in Global environment.
- Help, assist, resolve technical issues for flow/designs across all sites.
- Work with Design and flow teams to understand the drawbacks with the current flow/methodology. Propose new methodologies to reduce the design cycle time.
You are best equipped for this task if you have:
- BE / BTech / MS in Electronics with 8-12 years experience.
- Managed/Worked on multiple tapeouts at 90nm/65nm/40nm/28nm/16nm nodes complex designs.
- Working (hands on) knowledge on place & route, synthesis and STA for full chip complex designs.
- Strong experience in P&R, timing closure, synthesis, constraining and timing analysis required.
- Experience in Automotive and Industrial domain designs is desirable.
- Experience in low power/multi voltage design and understanding/development of UPF is a must.
- Excellent debugging skills to diagnose and devise workarounds for flow/design issues.
- Deep knowledge of Synopsys tools and flow is a must.
- Perl and TCL/TK required to achieve highly automated, reproducible and fast results.
- Knowledge about data management is a definite plus.
- Good team player working with geo-dispersed cross cultural and cross functional teams.
- Good communication and interpersonal skills required.
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design
Role Category: Programming & Design
Role: Team Lead/Technical Lead
Does this sound like just the right challenge for you? If so, we look forward to getting to know you!
UG: B.Tech/B.E. - Electronics/Telecommunication
PG: M.Tech - Electronics/Telecommunication
Doctorate: Doctorate Not Required